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lc 2 mos quad 8-bit dac with separate reference inputs ad7225 rev. c information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2010 analog devices, inc. all rights reserved. features four 8-bit dacs with output amplifiers separate reference input for each dac microprocessor compatible with double-buffered inputs simultaneous update of all 4 outputs operates with single or dual supplies extended temperature range operation no user trims required skinny 24-lead pdip, cerdip, soic, and ssop packages 28-lead plcc package functional block diagram v ref a v ref b v ref c v ref d v dd ldac v ss agnd dgnd input latch a dac latch a v out a dac a a input latch b dac latch b v out b dac b b input latch c dac latch c v out c dac c c input latch d control logic dac latch d v out d dac d d data bus db7 data (8-bit) db0 wr a1 a2 ad7225 00986-001 figure 1. general description the ad7225 contains four 8-bit voltage output digital-to- analog converters, with output buffer amplifiers and interface logic on a single monolithic chip. each dac has a separate reference input terminal. no external trims are required to achieve full specified performance for the part. the double-buffered interface logic consists of two 8-bit registers per channelan input register and a dac register. control input a0 and control input a1 determine which input register is loaded when wr goes low. only the data held in the dac registers determines the analog outputs of the converters. the double-buffering allows simultaneous update of all four outputs under control of ldac . all logic inputs are ttl and cmos (5 v) level compatible, and the control logic is speed compatible with most 8-bit microprocessors. specified performance is guaranteed for input reference voltages from 2 v to 12.5 v when using dual supplies. the part is also specified for single-supply operation using a reference of 10 v. each output buffer amplifier is capable of developing 10 v across a 2 k load. the ad7225 is fabricated on an all ion-implanted, high speed, linear-compatible cmos (lc 2 mos) process, which is specifically developed to integrate high speed digital logic circuits and precision analog circuitry on the same chip. product highlights 1. dacs and amplifiers on cmos chip. the single-chip design of four 8-bit dacs and amplifiers allows a dramatic reduction in board space requirements and offers increased reliability in systems using multiple converters. its pinout is aimed at optimizing board layout with all analog inputs and outputs at one end of the package and all digital inputs at the other. 2. single- or dual-supply operation. the voltage-mode configuration of the ad7225 allows single-supply operation. the part can also be operated with dual supplies, giving enhanced performance for some parameters. 3. versatile interface logic. the ad7225 has a common 8-bit data bus with individual dac latches, providing a versatile control architecture for simple interface to microprocessors. the double-buffered interface allows simultaneous update of the four outputs. 4. separate reference input for each dac. the ad7225 offers great flexibility in dealing with input signals, with a separate reference input provided for each dac and each reference having variable input voltage capability.
ad7225 rev. c | page 2 of 24 table of contents features .............................................................................................. 1 ? functional block diagram .............................................................. 1 ? general description ......................................................................... 1 ? product highlights ........................................................................... 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? single supply ................................................................................. 4 ? absolute maximum ratings ............................................................ 5 ? esd caution .................................................................................. 5 ? pin configurations and function descriptions ........................... 6 ? typical performance characteristics ............................................. 7 ? terminology ...................................................................................... 8 ? circuit information .......................................................................... 9 ? digital-to-analog section ........................................................... 9 ? op amp section ........................................................................... 9 ? digital inputs section ...................................................................9 ? interface logic information .......................................................... 10 ? ground management and layout ................................................ 11 ? specification ranges ...................................................................... 12 ? unipolar output operation .......................................................... 13 ? bipolar output operation ............................................................. 14 ? agnd bias ...................................................................................... 15 ? ac reference signal ....................................................................... 16 ? applications information .............................................................. 17 ? programmable transversal filter ............................................. 17 ? digital word multiplication ..................................................... 18 ? microprocesser interface ............................................................... 19 ? v ss generation ................................................................................ 20 ? outline dimensions ....................................................................... 21 ? ordering guide .......................................................................... 23 ? revision history 3/10rev. b to rev. c updated format .................................................................. universal deleted 28-terminal leadless ceramic chip carrier package ................................................................................. universal added 24-lead ssop package .......................................... universal changes to features section............................................................ 1 changes to table 1 ............................................................................ 3 changes to table 2 ............................................................................ 4 changes to table 3 ............................................................................ 5 changes to pin configurations and function descriptions section ................................................................................................ 6 added table 4; renumbered sequentially .................................... 6 changes to specification ranges section .................................... 12 changes to programmable transversal filter section and figure 21 .......................................................................................... 17 updated outline dimensions ....................................................... 21 changes to ordering guide .......................................................... 23
ad7225 rev. c | page 3 of 24 specifications v dd = 11.4 v to 16.5 v, v ss = ?5 v 10%; agnd = dg nd = 0 v; v ref x = +2 v to (v dd ? 4 v) 1 parameter , unless otherwise noted. all specifications t min to t max , unless otherwise noted. table 1. k, b versions 2 l, c versions 2 unit con ditions/comments static performance resolution 8 8 bits total unadjusted error 2 1 lsb max v dd = 15 v 5%, v ref = 10 v relative accuracy 1 1/2 lsb max differential nonlinearity 1 1 lsb max guaranteed m onotonic full -sc ale error 1 1/2 lsb max full - scale temp erature coeff icient 5 5 ppm/ c typ v dd = 14 v to 16.5 v, v ref = 10 v zero code error 30 20 mv max zero code error temperature coefficient 30 30 v/c typ reference input voltage range 2 to (v dd ? 4) 2 to (v dd ? 4) v min to v max input resistance 11 11 k min input capacitance 3 50 50 pf max occurs when each dac is loaded with all 1s channel -to - channel isolation 3 60 60 db min v ref = 10 v p -p s ine w ave at 10 khz ac feedthrough 3 ?70 ?70 db max v ref = 10 v p -p s ine wave at 10 khz digital inputs input high voltage, v inh 2.4 2.4 v min input low voltage, v inl 0.8 0.8 v max input leakage current 1 1 a max v in = 0 v or v dd input capacitance 3 8 8 pf max input coding binary binary dynamic perfor mance voltage output slew rate 3 2.5 2.5 v/ s min voltage output settling time 3 4 4 s max v ref = 10 v; s ettling t ime to ? lsb digital feedthr ough 3 50 50 nv sec typ code transition all 0s to all 1s digital crosstalk 3 50 50 nv sec typ code transition all 0s to all 1s minimum load resistance 2 2 k min v out = 10 v power supplies v dd range 11.4/16.5 11.4/16.5 v min to v max for s pecified p erformance i dd 10 10 ma max outputs unloaded; v in = v inl or v inh i ss 9 9 ma max outputs unloaded; v in = v inl or v inh switching characteristics 3 , 4 t 1 50 50 ns min write pulse width t 2 0 0 ns min address to write setup time t 3 0 0 ns min address to write hold time t 4 50 50 ns min data valid to write setup time t 5 0 0 ns min data valid to write hold time t 6 50 50 ns min load dac pulse width 1 maximum possible reference voltage. 2 temperature range is as follows for all versions: ?40c to +85c . 3 sample tested at 25c to ensure compliance. 4 switching characteristics apply for single - supply and dual - supply operation.
ad7225 rev. c | page 4 of 24 s ingle s upply v dd = 15 v 5%; v ss = agnd = dgnd = 0 v; v ref x = 10 v, unless otherwise noted. all specifications t min to t max , unless otherwise noted. table 2. parameter k, b versions 1 l, c versions 1 unit conditions/comments static performance resolution 8 8 bits total unadjusted error 2 2 1 lsb max differential nonlinearity 2 1 1 lsb max guaranteed m onotonic reference input voltage range 2 to (v dd ? 4) 2 to (v dd ? 4) v min to v max input resistance 11 11 k min input capacitance 3 50 50 pf max occurs when each dac is loaded with all 1s channel -to - channel isolation 2 , 3 60 60 db min v ref = 10 v p - p sine wave at 10 khz ac feedthrough 2 , 3 ?70 ?70 db max v ref = 10 v p - p sine wave at 10 khz digital inputs input high voltage, v inh 2.4 2.4 v min input low voltage, v inl 0.8 0.8 v max input leakage current 1 1 a max v in = 0 v or v dd input capacitance 3 8 8 pf max in put coding binary binary dynamic performance voltage output slew rate 3 2 2 v/ s min voltage output settling time 3 4 4 s max digital fee dthrough 2 , 3 10 10 nv sec typ code transition all 0s to all 1s digital crosstalk 2 , 3 10 10 nv sec typ code transition all 0s to all 1s minimum load resistance 2 2 k min v out = 10 v power supplies v dd range 14.25/15.75 14.25/15.75 v min to v max for specified performance i dd 10 10 ma max outputs unloaded; v in = v inl or v inh switching characteristics 3 t 1 50 50 ns min write pulse width t 2 0 0 ns min address to write setup time t 3 0 0 ns min address to write hold time t 4 50 50 ns min data valid to write setup time t 5 0 0 ns min data valid to write hold time t 6 50 50 ns min load dac pulse width 1 temperature range is as follows for all versions : ?40c to +85c . 2 sample tested at 25c to ensure compliance. 3 switching characteristics apply for single - supply and dual - supply operation.
ad7225 rev. c | page 5 of 24 absolute maximum rat ings table 3. parameter rating v dd to agnd ? 0.3 v, +17 v v dd to dgnd ? 0.3 v, +17 v v dd to v ss ? 0.3 v, +24 v agnd to dgnd ? 0.3 v, v dd digital input voltage to dgnd ? 0.3 v, v dd + 0.3 v v ref x to agnd ? 0.3 v, v dd + 0.3 v v out x to agnd 1 v ss , v dd power dissipation (any package) to 75 c 500 mw der ates above 75 c by 2.0 mw/ c operating temperature commercial (k, l versions) ?40 c to +85 c industrial (b, c versions) ?40 c to +85 c storage temperature ?65 c to +150 c lead temperature (soldering, 10 sec) 300c 1 outputs can be shorted to any vo ltage in the range v ss to v dd provided that the power dissipation of the package is not exceeded. typical short - circuit current for a short to agnd or v ss is 50 ma. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
ad7225 rev. c | page 6 of 24 pin configuration s and function descrip tions v out b 1 v out a 2 v ss 3 v ref b 4 v out c 24 v out d 23 v dd 22 v ref c 21 v ref a 5 v ref d 20 agnd 6 a0 19 dgnd 7 a1 18 ldac 8 wr 17 db7 9 db0 16 db6 10 db1 15 db5 11 db2 14 db4 12 db3 13 ad7225 top view (not to scale) 00986-002 1 28 27 26 234 5 6 7 8 9 10 11 25 24 23 22 21 20 19 nc = no connect v ref b v ref a agnd nc dgnd ldac db7 v ref c v ref d a0 nc a1 wr db0 v ss v out a v out b nc v out c v out d v dd db6 db5 db4 nc db3 db2 db1 pin 1 indentfier 12 13 14 15 16 17 18 ad7225 top view (not to scale) 00986-003 figure 2 . pdip, soic, cerdip, and ssop figure 3 . plcc table 4 . pin f unction descriptions pin no. neonic description pdip soic cerdip ssop pcc 1 2 v out b dac channe l b voltage output. 2 3 v out a dac channe l a voltage output. 3 4 v ss negative power supply connection. 4 5 v ref b reference voltage connection for da c channel b. 5 6 v ref a reference voltage connection for dac channel a. 6 7 agnd analog ground reference connectio n. 7 9 dgnd digital ground reference connection. 8 10 ldac active low load dac signal . dac register d ata is latched on th e rising edge of ldac . 9 11 db7 data bit 7 ( most significant data bit) . 10 12 db6 data bit 6. 11 13 db5 data bit 5. 12 14 db4 data bit 4. 13 16 db3 data bit 3. 14 17 db2 data bit 2. 15 18 db1 data bit 1. 16 19 db0 data bit 0 (leas t significant data bit ). 17 20 wr active low data write signal . input register data is latched on the rising edge of wr . 18 21 a1 dac address select pin . 19 23 a0 dac address select pin . 20 24 v ref d reference voltage connection for dac channel d. 21 25 v ref c reference voltage connection for dac channel c. 22 26 v dd positive power supply connection. 23 27 v out d dac channel d voltage output. 24 28 v out c dac channel c voltage output. n/a 1, 8, 15, 22 nc no internal connection .
ad7225 rev. c | page 7 of 24 typical performance characteristics t a = 25 c, v dd = 15 v, v ss = ? 5 v, unless otherwise noted. 1.0 ?1.0 ?0.5 0 0.5 0 32 64 96 128 160 192 224 total unadjusted error (lsb) input code v ref x = 10v 00986-004 figure 4 . channel - to - channel matching 1.0 ?1.0 ?0.5 0 0.5 0 1 2 3 4 5 6 7 8 9 10 11 12 13 relative accuracy (lsb) v ref (v) v dd = 5v v dd = 12v v dd = 15v 00986-005 figure 5 . relative accuracy vs. v ref 0.50 ?0.50 ?0.25 0 0. 25 0 1 2 3 4 5 6 7 8 9 10 11 12 13 differential nonlinearity (lsb) v ref (v) v dd = 5v v dd = 12v v dd = 15v 00986-006 figure 6 . differential nonlinearity vs. v ref 8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 6 7 ?60 ?40 ?20 0 20 40 60 80 100 120 140 power supply current (ma) temperature (c) i dd i ss 00986-007 figure 7 . power supply current vs. temperature 5 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 ?60 ?40 ?20 0 20 40 60 80 100 120 140 zero code error (mv) temperature (c) v out a v out b v out c v out d 00986-008 figure 8 . zero code error vs. temperature 100 90 10 0% 1ms/div 300v 00986-009 figure 9 . broadband noise
ad7225 rev. c | page 8 of 24 terminology total unadjusted error tot a l u nadjusted e rror is a comprehensive specification that includes full - scale error, relative accuracy, and zero code error. maximum output voltage is v ref ? 1 lsb (ideal), where 1 lsb (ideal) is v ref /256. the lsb size var ies over the v ref range. therefore, the zero code error, relative to the lsb size, increase s as v ref decreases. accordingly, the total unadjusted error, which includes the zero code error, a lso var ies in terms of lsb over the v ref range. as a result, total unadjusted error is specified for a fixed reference voltage of 10 v. relative accuracy relative a ccuracy or endpoint nonlinearity is a measure of the maximum deviation from a straight line passing through the endpoints of the dac transfer function. it is measured after allowing for zero code error and full - scale error and is normally expressed in lsb or as a percentage of full - scale reading. differential nonlinearity differential n onlinearit y is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specifie d differential nonlinearity of 1 lsb max imum over the operating temperature range ensures monotonicity. digital feedthrough digital f eedt hrough is the glitch impulse transferred to the output of the dac due to a change in its digital input code. it is specified in nv sec and is measured at v ref = 0 v. digital crosstalk digital c rosstalk is the glitch impulse transferred to the output of on e converter (not addressed) due to a change in the digital input code to another addressed converter. it is specified in nv sec and is measured at v ref = 0 v. ac feedthrough ac f eedthrough is the proportion of reference input signal that appears at the out put of a converter when that dac is loaded with all 0s. channel -to - channel isolation channel - to - channel isolation is the proportion of input signal from the reference of one dac (loaded with all 1s) that appears at the output of one of the other three dacs (loaded with all 0s) the figure given is the worst case for the three other outputs and is expressed as a ratio in db. full - scale error full -s cale e rror is defined as fse = measured value ? zero code error ? ideal value
ad7225 rev. c | page 9 of 24 circuit information d igital - to- analog section the ad7225 contains four identical, 8 - bit voltage mode digital - to - analog converters. each dac has a separate reference input. the output voltages from the converters have the same polarity as the reference voltages, allowing single - supply operation. a novel dac switch pair arrangement on the ad7225 allows a refer - ence voltage range from 2 v to 12.5 v on each reference input. each dac consists of a highly stable, thin - film, r - 2r ladder and eight high speed nmos, single - pole, double - throw sw itches. the simplified circuit diagram for channel a is shown in figure 10 . note that agnd is common to all four dacs. v out a 2r db7 2r db6 2r db5 2r 2r db0 r r r v ref a agnd shown for all 1s on dac 00986-010 figure 10 . d igital -to - analog simplified circuit diagram the input im pedance at any of the reference inputs is code de pendent and can vary from 11 k minimum to infinity. the lowest input impedance at any reference input occurs when that dac is loaded with digital code 01010101. therefore, it is important that the reference presents a low output impedance under changing load conditions. the nodal capa citance at the reference terminals is also code dependent and typically varies from 15 pf to 35 pf. each v out x pin can be considered a digitally programmable voltage source with an output voltage of v outx = d x v refx where d x is a fractional representat ion of the digital input code and can vary from 0 to 255/256. the output impedance is that of the output buffer amplifier. op amp section each voltage mode d ac output is buffered by a unity gain noninverting cmos amplifier. this buffer amplifier is capable of developing 10 v across a 2 k load and can drive capacitive loads of 3300 pf. the ad7225 can be operated single or dual supply; operating with dual supplies results in enhanced performance in some parameters that cannot be achieved with single - supply opera - tion. in single - supply oper ation (v ss = 0 v = agnd), the sink capability of the am plifier, which is normally 400 a, is reduced as the output voltage nears agnd. the full sink capability of 400 a is maintained over the full output voltage range by tying v ss to ? 5 v. this is shown i n figure 11. settling time for negative - going output signals approaching agnd is similarly affected by v ss . negative - going settling time for single - supply operation is longer than for dual - supply opera - tion. positi ve- going settling time is not affected by v ss . 500 400 300 200 100 0 0 10 8 6 4 2 i sink (a) v out (v) v ss = ?5v v ss = 0v v dd = +15v t a = 25c 00986-011 figure 11 . variation of i sink with v out additionally, the negative v ss gives more headroom to the output amplifiers, which results in better zero code perfor - mance and improved slew rate at the output than can be obtained in the single - supply mode. digital inputs secti on the ad7225 digital inputs are compatible with either ttl or 5 v cmos levels. all logic inputs are static protected mos gates with typical input currents of less than 1 na. internal input protection is achieved by an on - chip distributed diode between dgnd and each mos gate. to minimize power supply currents, it is recommended that the digital input voltages be driven as close to the supply rails (v dd and dgnd) as practi - cally possible.
ad7225 rev. c | page 10 of 24 interface logic info rmation the ad7225 contains two registers per dac, an input register and a dac register. the a0 and a1 address l ines select which input register accept s data from the input port. when the wr signal is low, the input latches of the selected dac are transpa - rent. the data is latched into the addressed input register on the rising edge of table 5 wr . shows the addressing for the input registers on the ad7225. table 5 . ad7225 addressing a1 a0 selected input register l ow low dac a low h igh dac b h igh low dac c h igh h igh dac d only the data held in the dac register determines the analog output of the conver ter. the ldac signal is common to all four dacs and controls the transfer of information from the input registers to the dac registers. data is latched into all four dac registers simultaneously on the rising edge of ldac . the ldac signal is level triggered and therefore the dac registers can be made transparent by tying ldac low (in this case, the outputs of the converters respond to the data held in their respective input latches). ldac is an asynchronous signal and is indepen - dent of wr . this is useful in many applications. however, in systems where the asynchronous ldac can occur during a write cycle (or vice versa), care must be taken to ensure that incorrect data is not latched through to the output . if ldac is activated prior to the rising edge of wr (or wr occurs during ldac ), ldac must st ay low for t 6 or longer after wr table 6 . truth table goes high to ensure correct data is latched through to the output. tabl e 6 shows the truth table for ad7225 operation. figure 12 shows the input control logic for the part; the write cycle timing diagram is given in fig ure 13 . wr ldac function h igh high no o peration. device not selected. l ow high input r egister of s elected dac t ransparent. high input r egister of s elected dac l atched. high low all f our dac r egisters transparent ( that is , outputs respond to data held in respective input registers). input registers are latched. high all f our dac r egisters l atched. low low dac registers and selected input register transparent output follows input data for selected channel. to input latch a to input latch b to all dac latches to input latch c to input latch d ldac a0 a1 wr 00986-012 figure 12 . input control logic address data in ldac wr 5v 5v 5v 0v 5v 0v data valid v inh v inl t 2 t 3 t 1 t 6 t 5 t 4 notes 1. all input signal rise and fall times measured from 10% to 90% of 5v. t r = t f = 20ns over v dd range. 2. timing measurement reference level is 3. if ldac is activated prior to the rising edge of wr, then it must stay low for t 6 or longer after wr goes high. v inh + v inl 2 00986-013 fig ure 13 . write cycle timing diagram
ad7225 rev. c | page 11 of 24 g round management and layout because the ad7225 contains four reference inputs that can be driven from ac sources (see the ac r eference s ignal sectio n), careful layout and grounding is important to minimize analog crosstalk between the four channels. the dynamic performance of the four dacs depends on the optimum choice of board layout. figure 14 shows the rela tionship between input fre - quency and channel - to - channel isolation. figure 15 shows a printed circuit board layout that minimizes cross talk and feedthrough. the four input signals are screened by agnd. v ref was li mited to between 2 v and 3.24 v to avoid slew rate limiting effects from the output amplifier during measurements. ?80 ?70 ?60 ?50 ?40 ?30 20k 50k 100k 200k 500k 1m isolation (db) input frequency (hz) v dd = +15v v ss = ?5v t a = 25c v ref = 1.24v p-p 00986-014 figure 14 . channel - to - channel isolation v out c v out b v out d v out a v dd v ss v ref c v ref b v ref d v ref a msb lsb pin 1 system gnd dgnd agnd 00986-015 figure 15 . suggested pcb layout for ad7225 , com ponent side (top view)
ad7225 rev. c | page 12 of 24 s pecification r anges for the ad7225 to operate to rated specifications, its input reference voltage must be at least 4 v below the v dd power supply voltage. this voltage differential is the overhead voltage required by the output amplifiers. the ad7225 is specified to opera te over a v dd range from 12 v 5% to 15 v 10% ( that is , from 11.4 v to 16.5 v) with a v ss of ?5 v 10%. operation is als o specified for a single 15 v 5% v dd supply. applying a v ss of ? 5 v results in improv ed zero - code error, improved output sink capability with outputs near agnd, and improved negative - going settling time. performance is specified over a wide range of reference voltages from 2 v to (v dd ? 4 v) with dual supplies. this allows a range of stand ard reference generators to be used , such as the ad780 , a 2.5 v band gap reference, and the ad584 , a precision 10 v reference. note that an output voltage range of 0 v to 10 v requires a nominal 15 v 5% power supply voltage .
ad7225 rev. c | page 13 of 24 u nipolar o utput o peration this is the basic mode of operation for each channel of the ad7225, with the output voltage having the same positive polarity as v ref x . the ad7225 can be operated si ngle supply (v ss = agnd) or with positive/negative supplies (see the op amp section , which outlines the advantages of having negative v ss ). connections for the unipolar output operation are shown in figure 16 . the voltage at any of the reference inputs must never be negative with respect to dgnd. failure to observe this precaution may cause parasitic transistor action and possible device destruction. the code table for unipo lar output operation is shown in table 7 . note, ( ) ( ) ? ? ? ? ? ? = = ? 256 1 2 1 8 ref ref v v lsb v ref a v ref b v ref c v ref d v dd v ss agnd dgnd v out a dac a v out b dac b v out c dac c v out d dac d db7 (msb) db0 (lsb) a1 a2 wr ldac ad7225 00986-016 figure 16 . unipolar output circuit table 7 . unipolar code table dac latch contents analog o utput msb lsb 1111 1111 ( ) 256 255 ref v + 1000 0001 ( ) 256 129 ref v + 1000 0000 ( ) 2 256 128 ref ref v v += + 0111 1111 ( ) 256 127 ref v + 0000 0001 ( ) 256 1 ref v + 0000 0000 0 v
ad7225 rev. c | page 14 of 24 b ipolar o utput o peration each of the dacs of the ad7225 can be individually confi - gured to provide bipolar output operation. this is possible using one external amplifier and two resistors per channel. figure 17 shows a circuit used to implement offset binar y coding (bipolar operation) with dac a (dac channel a) of the ad7225. in this case, ( ) ( ) ref ref a out v r r2 vd r1 r2 v ? ? ? ? ? ? ? ? ? ? ? ? ? += 1 1 with r1 = r2 ( ) ( ) ref a out v dv ?= 12 where d a is a fractional representation of the digital word in latch a (0 d a 255/256). mismatch between r1 and r2 causes gain and offset errors and, therefore, these resistors must match and track over tempera - ture. t he ad7225 can be operated in single supply or from positive/negative supplies. table 8 shows the digital code vs . output voltage relationship for the circuit of figure 17 with r1 = r2. +15v ?15v v dd v ss agnd dgnd v out a dac a ad7225* v ref a r2 v out r1 v ref r1, r2 = 10k ? 0.1%. *digital inputs omitted for clarity. 00986-017 figure 17 . bipolar output circuit table 8. bipolar (offset binary) code table dac latch contents analog output msb lsb 1111 1111 ( ) 128 127 ref v + 1000 0001 ( ) 128 1 ref v + 1000 0000 0 v 0111 1111 ( ) 128 1 ref v ? 0000 0001 ( ) 128 127 ref v ? 0000 0000 ( ) ref ref v v ?= ? 1 128 128
ad7225 rev. c | page 15 of 24 agnd b ias the ad7225 agnd pin can be biased above system ground (ad7225 d gnd) to provide an offset zero analog output voltage level. figure 18 shows a circuit configuration to achieve this for dac ch annel a of the ad7225. the output voltage, v out a, can be expressed as: v out a = v bias + d a ( v in ) where d a is a fractional representation of the digital word in dac latch a (0 d a 255/256). v dd v ss agnd v bias v in dgnd v out a dac a ad7225* v ref a *digital inputs omitted for clarity. 00986-018 figure 18 . agnd bias circuit for a given v in , increasing agnd above system ground reduce s the effective v dd ? v ref , which must be at least 4 v to ensure specified operation. note that , because the agnd pin is common to all four dacs, this method biases up the output voltages of all the dacs in the ad7225. note that v dd and v ss of the ad7225 should be referenced to dgnd.
ad7225 rev. c | page 16 of 24 ac r eference s ignal in some applications, it may be desirable to have ac reference sig nals. the ad7225 has multiplying capability within the upper (v dd ? 4 v) and lower (2 v) limits of reference voltage when operated with dual supplies. therefore, ac signals need to be ac - coupled and biased up before being applied to the reference inputs. figure 19 shows a sine wa ve signal applied to v ref a. for input signal frequencies up to 50 khz, the output distortion typically remains less than 0.1%. the typical 3 db bandwidth figure for small signal inputs is 800 khz. *digital inputs omitted for clarity. v dd v ss agnd dgnd v out a dac a ad7225* v ref a +15v +15v 15k? 10k? +4v ?4v reference input 00986-019 figure 19 . applying an ac signal to the ad7225
ad7225 rev. c | page 17 of 24 a pplications information h 1 1 t x n h 2 2 t x n ? 1 h 3 3 t x n ? 2 h 4 4 x n ? 3 filter input + y(n) filter output ad7225 quad dac + ad585 sha ad7225 quad dac ad7820 adc input samples am29520 tlc delayed input samples ad584 ref 10v v ref am7224 dac v out v ref v ref a v out a h 1 v ref a v out a h 2 v ref a v out a h 3 v ref a v out a h 4 tap weight gain set v out a v out b v out c v out d accumulator output filter output 00986-020 figure 20 . programmable transversal filter programmable transversal filter a discrete time filter can be described by either multiplication in the frequency domain or by convolution i n the time domain : ( ) ( ) ( ) = +? =?= 1 1 the convolution sum can be implemented using the special struc - ture known as the transversal filter ( see figure 21 ). i t consists of an n - stage delay line with n taps weig hted by n coefficients, the resulting products being accumulated to form the output. the tap weights or coefficients h k are the nonzero elements of the impulse response and therefore determine the filter transfer function. a particular filter frequency res ponse is realized by setting the coefficients to the appropriate values. this property leads to the implementation of transversal filters whose fre - quency response is programmable. h 1 1 t x n h 2 2 t x n ? 1 h 3 3 x n ? 2 h n n x n ? n + 1 h n ? 1 n ?1 t x n ? n filter input + x n ? k + 1 h k y n = n k = 1 filter output 00986-021 figure 21 . transversal filter a four - tap program mable transversal filter can be implemented using the ad7225 ( see figure 20 ). the input signal is first sampled and converted to allow the tapped delay line function to be provided by the a m 29520. the multiplication of delayed input samples by fixed, programmable up weights is accom plished by the ad7225, the four coefficients or reference inputs being set by the digital codes stored in the ad7226. the resultant products are accumulated to yi eld the convolution sum output sample, which is held by the ad585 . 0 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0. 05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 gain (db) normalized frequency (f/f s ) h 1 = 0.117 h 2 = 0.417 h 3 = 0.417 h 4 = 0.417 00986-022 figure 22 . predicted (theoretical) response 0 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0. 05 0.10 0. 15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 gain (db) frequency (f/f s ) h 1 (dac a) = 00011110 h 2 (dac b) = 01101011 h 3 (dac c) = 01101011 h 4 (dac d) = 00011110 00986-023 figure 23 . actual response low - pass, band - pass , and high - pass filters can be synthesized using this arrangement. the particular up weights needed for any desired transfer function can be obtained using the standard remez e xchange algorithm. figure 22 shows the theoretical low - pass frequency response produced by a four - tap transversal filter with the coefficients indicated. although the theoretical prediction does not take into account the quantization of the input samples and the truncation of the coefficients, neverthe -
ad7225 rev. c | page 18 of 24 less , there exists a good correlation with the actual performance of the transversal filter ( see figure 23). digital word multiplication because each dac of the ad7225 has a separate reference input, the output of one dac can be used as the reference input for another. this means that multiplication of digital words can be performed (with the result given in analog form). for example , if the output from dac a is applied to v ref b, then the output from dac b , v out b, can be expressed as: v out b = d a d b v ref a where d a and d b are the fractional representations of the digital words in dac latch a and dac latch b, respectively. if d a = d b = d, the result is d 2 v ref a. in this manner, the four dacs can be used on their own or in conjunction with an external summing amplifier to generate complex waveforms. figure 24 shows one such application. in this case, the output waveform, y, is represented by y = ?( x 4 + 2 x 3 + 3 x 2 + 2 x + 4) v in where x is the digital code that is applied to all four dac latches. *digital inputs omitted for clarity. 100k? y v out a v ref a v out b v ref b v out c v ref c v out d v ref d v ss agnd dgnd 15v v dd ad7225* v in 100k? 50k? 33k? 50k? 25k? 00986-024 figure 24 . complex waveform generation
ad7225 rev. c | page 19 of 24 m icroprocesser interf ace *linear circuitry omitted for clarity. address decode latch en ad7225 * a0 a1 db7 db0 ldac wr address bus address data bus 8085a/ 8088 a15 a8 ale ad0 ad7 wr 00986-025 *linear circuitry omitted for clarity. z-80 a15 a8 d0 d7 ad7225 * wr a0 a1 db7 db0 ldac wr address bus data bus address decode en mreq 00986-026 figure 25 . ad7225 - to - 8085a/8 088 interface, double - buffered mode figure 26 . ad7225 - to -z- 80 interface, double - buffered mode *linear circuitry omitted for clarity. 6809/ 6502 a15 a0 e or 2 d0 d7 ad7225 * r/w a0 a1 db7 db0 ldac wr address bus data bus address decode en 00986-027 *linear circuitry omitted for clarity. 68008 a23 a1 d0 d7 ad7225* a0 a1 db7 db0 ldac wr address bus data bus address decode en as r/w dtack 00986-028 figure 27 . ad7225 - to - 6809/6502 interface, single - buffered mode figure 28 . ad7225 - to - 68008 interface, single - buffered mode
ad7225 rev. c | page 20 of 24 v ss g eneration operating the ad7225 from dual supplies results in enhanced performance over single - supply operation on a number of parameters as previously outlined. some applications may require this enhance d performance, but may only have a single power supply rail available. the circuit of figure 29 shows a method of generating a negative voltage using one cd4049, operated from a v dd of 15 v. two inverters of the he x inverter chip are used as an oscillator. the other four inverters are in parallel and used as buffers for higher output current. the square wave output is level translated to a negative - going signal, then rectified and filtered. the circuit configuration shown provide s an output voltage of ? 5.1 v for current loadings in the range of 0.5 ma to 9 ma. this satisfies the ad7225 i ss require - ment over the commercial operating temperature range. 1/6 cd4049ae 1/6 cd4049ae 1/6 cd4049ae 1/6 cd4049ae 1/6 cd4049ae 1/6 cd4049ae 510k? 5.1k ? + 0.02f 47f 47f 5v1 ?v out + + 1n4001 1n4001 510? 00986-029 figure 29 . v ss generation circuit
ad7225 rev. c | page 21 of 24 outline dimensions controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. corner leads may be configured as whole or half leads. compliant to jedec standards ms-001 071006-a 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 0.150 (3.81) 0.130 (3.30) 0.115 (2.92) 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) 24 1 12 13 0.100 (2.54) bsc 1.280 (32.51) 1.250 (31.75) 1.230 (31.24) 0.210 (5.33) max seating plane 0.015 (0.38) min 0.005 (0.13) min 0.280 (7.11) 0.250 (6.35) 0.240 (6.10) 0.060 (1.52) max 0.430 (10.92) max 0.014 (0.36) 0.010 (0.25) 0.008 (0.20) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.015 (0.38) gauge plane 0.195 (4.95) 0.130 (3.30) 0.115 (2.92) figure 30. 24-lead plastic dual in-line package [pdip] narrow body (n-24-1) dimensions shown in inches and (millimeters) controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. 24 112 13 0.310 (7.87) 0.220 (5.59) 0.005 (0.13) min 0.098 (2.49) max 15 0 0.320 (8.13) 0.290 (7.37) 0.015 (0.38) 0.008 (0.20) seating plane 0.200 (5.08) max 1.280 (32.51) max 0.150 (3.81) min 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.100 (2.54) bsc 0.070 (1.78) 0.030 (0.76) 0.060 (1.52) 0.015 (0.38) pin 1 100808-a figure 31. 24-lead ceramic dual in-line package [cerdip] narrow body (q-24-1) dimensions shown in inches and (millimeters)
ad7225 rev. c | page 22 of 24 compliant to jedec standards mo-047-ab controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. 4 5 26 25 11 12 19 18 top view (pins down) sq 0.456 (11.582) 0.450 (11.430) 0.050 (1.27) bsc 0.048 (1.22) 0.042 (1.07) 0.048 (1.22) 0.042 (1.07) 0.495 (12.57) 0.485 (12.32) sq 0.021 (0.53) 0.013 (0.33) 0.430 (10.92) 0.390 (9.91) 0.032 (0.81) 0.026 (0.66) 0.120 (3.04) 0.090 (2.29) 0.056 (1.42) 0.042 (1.07) 0.020 (0.51) min 0.180 (4.57) 0.165 (4.19) bottom view (pins up) 0.045 (1.14) 0.025 (0.64) r pin 1 identifier 042508- a figure 32 . 28 - lead plastic leaded chip carrier [plcc] (p - 28) dimensions shown in inches and (millimeters) compliant to jedec standards ms-013-ad controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. 15.60 (0.6142) 15.20 (0.5984) 0.30 (0.0118) 0.10 (0.0039) 2.65 (0.1043) 2.35 (0.0925) 10.65 (0.4193) 10.00 (0.3937) 7.60 (0.2992) 7.40 (0.2913) 0.75 (0.0295) 0.25 (0.0098) ? 45 1.27 (0.0500) 0.40 (0.0157) coplanarity 0.10 0.33 (0.0130) 0.20 (0.0079) 0.51 (0.0201) 0.31 (0.0122) seating plane 8 0 24 13 12 1 1.27 (0.0500) bsc 06-07-2006-a figure 33 . 24 - lead standard small outline package [ soic_w] wide body (rw - 24) dimensions shown in millimeters and (inches)
ad7225 rev. c | page 23 of 24 compliant t o jedec s t andards mo-150-ag 060106- a 24 13 12 1 8.50 8.20 7.90 8.20 7.80 7.40 5.60 5.30 5.00 sea ting plane 0.05 min 0.65 bsc 2.00 max 0.38 0.22 coplanarit y 0.10 1.85 1.75 1.65 0.25 0.09 0.95 0.75 0.55 8 4 0 figure 34 . 24 - lead shrink small outline package [ssop] (rs - 24) dimensions shown in millimeters ordering guide model 1 , 2 temperature range total unadjusted er ror package description package option ad7225bq ?40c to +85c 2 lsb 24- lead cerdip q-24-1 ad7225brs ?40c to +85c 2 lsb 24- lead ssop rs-24 ad7225brs- reel ?40c to +85c 2 lsb 24- lead ssop rs-24 ad7225brsz ?40c to +85c 2 lsb 24- lead ssop rs-24 ad7225crs ?40c to +85c 1 lsb 24- lead ssop rs-24 ad7225crs- reel ?40c to +85c 1 lsb 24- lead ssop rs-24 ad7225crsz ?40c to +85c 1 lsb 24- lead ssop rs-24 ad7225crsz- rl ?40c to +85c 1 lsb 24- lead ssop rs-24 ad7225kn ?40c to +85c 2 lsb 24- lead pdip n-24-1 ad7225knz ?40c to +85c 2 lsb 24- lead pdip n-24-1 ad7225kp ?40c to +85c 2 lsb 28- lead plcc p-28 ad7225kp- reel ?40c to +85c 2 lsb 28- lead plcc p-28 ad7225kpz ?40c to +85c 2 lsb 28- lead plcc p-28 ad7225kr ?40c to +85c 2 lsb 24- lead soic_w rw-24 ad7225kr- reel ?40c to +85c 2 lsb 24- lead soic_w rw-24 ad7225krz ?40c to +85c 2 lsb 24- lead soic_w rw-24 ad7225krz- reel ?40c to +85c 2 lsb 24- lead soic_w rw-24 ad7225ln ?40c to +85c 1 lsb 24- lead pdip n-24-1 ad7225lnz ?40c to +85c 1 lsb 24- lead pdip n-24-1 ad7225lp ?40c to +85c 1 lsb 28- lead plcc p-28 ad7225lp- reel ?40c to +85c 1 lsb 28- lead plcc p-28 ad7225lpz ?40c to +85c 1 lsb 28- lead plcc p-28 ad7225lpz- reel ?40c to +85c 1 lsb 28- lead plcc p-28 ad7225lr ?40c to +85c 1 lsb 24- lead soic_ w rw-24 ad7225lr- reel ?40c to +85c 1 lsb 24- lead soic_w rw-24 ad7225lrz ?40c to +85c 1 lsb 24- lead soic_w rw-24 ad7225lrz- reel ?40c to +85c 1 lsb 24- lead soic_w rw-24 1 to order mil - std - 883 processed parts, add /883b to part number. contact your local sales office for military data sheet. 2 z = rohs compliant part.
ad7225 rev. c | page 24 of 24 notes ?2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d00986-0-3/10(c)

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